State-of the art digital X-ray imaging devices normally contain a scintillation layer, which converts at least one x-ray photon into visible light, and a photodiode array, which captures the visible image produced by the scintillation layer. Scintillating materials optimised for different X-ray energies are available. Therefore this approach is used for a wide variety of X-ray imaging applications. The efficiency of wavelength conversion in CsI(Tl) for example, a commonly used scintillation material, may be around 10%. This means that per keV of energy of an impinging X-ray photon one receives about 50 visible 2 eV photons (i.e., 100 eV). The subsequent conversion of the visible light into electron-hole pairs has normally an efficiency of below 50%, which yields about 25 electron-hole pairs per keV of X-ray energy.
In view of the relatively low efficiency of indirect conversion by way of scintillators, direct conversion of X-rays into electron-hole pairs would clearly be preferable. This is in fact possible by replacing the scintillator/photodetector combination by a suitable semiconductor structure.
When an X-ray photon is absorbed in a semiconductor, the photon's energy will be used to generate a number of electron-hole pairs. In the presence of an electric field the free electrons in the conduction band and the holes in the valence band will start to drift in opposite directions. For high enough quality of the semiconductor material, electron-hole pairs will be separated before they recombine. These charge carriers thus give rise to an electronic signal, the occurrence of which indicates absorption of an X-ray photon, and the strength of which is a measure of the photon's energy.
One of the most common detector materials is of course silicon, since it is the substrate material of most electronic circuits and therefore very well understood. Silicon based direct conversion X-ray imaging devices have been developed, e.g., by the Medipix collaboration (cf. http://medipix.web.cern.ch, visited on Aug. 14, 2008) or by Dectris AG (cf. http://www.dectris.ch, visited on Aug. 14, 2008). Such systems consist of one or several CMOS or CCD read-out chips, a silicon detection layer with suitable implantations on both sides to create an electric field when a voltage is applied across the substrate, and an intermediate connection layer which electrically connects every read-out pixel to the corresponding sensor pixel (see for example European Patent No. 0571135 to Collins et al., French Patent No. 2810453 to Pitault et al., and M. Bisogni et al., in IEEE Trans. Nucl. Sci. 51, 3081 (2004). However, in silicon one needs on average 3.6 eV to create one e-h pair (see for example Alig et al., “Scattering by ionization and phonon emission in semiconductors”, Phys. Rev. B 22, 5565 (1980); and in “Scattering by ionization and phonon emission in semiconductors. II. Monte Carlo calculations” Phys. Rev. B 27, 968 (1983), which leads to 280 e-h pairs per keV of X-ray energy. The conversion efficiency is therefore more than ten times higher than in a scintillator-photodiode setup.
Schwarz et al. disclose in “Measurements with Si and GaAs pixel detectors bonded to photon counting readout chips”, Nucl. Instr. Meth. A 466, 87 (2001) an absorption layer employing Gallium Arsenide (GaAs), which has a higher Z-number than Silicon.
Street et al. in “Comparative Study of PbI2 and HgI2 as Direct Detector Materials for High Resolution X-ray Image Sensors”, Proc. of SPIE, Vol. 4320, pp. 1 (2001), report the properties of HgI2 and PbI2, as candidate materials for future direct detection X-ray image sensors.
EP patent 1,391,940 (Moryiama et al.) discloses a semiconductor radiation detector element of Schottky barrier type, comprising: a compound semiconductor crystal including cadmium and tellurium as main components; and voltage application means for applying voltage to the compound semiconductor crystal.
International patent application WO02/067271 (Ruzin) discloses an imaging and particle detection system using silicon enriched by heavier elements. More specifically, a Si absorption layer is alloyed with an enrichment material, such as germanium. The resulting alloys, e.g., Si1-xGex, are proposed to be bulk grown. The x content of Ge has been proposed to be kept below 20%.
U.S. Pat. No. 5,712,484 (Hideo et al.) discloses a germanium detector measuring an energy spectrum of gamma ray flux. The detector includes a copper cooling layer continuous over a periphery of the columnar germanium crystal.
WO 2005/079199A2 (King et al.) discloses an image sensor comprising an array of germanium photosensitive elements integrated with a silicon substrate and integrated with silicon readout circuits. The silicon transistors are formed first on a silicon substrate, using well known silicon wafer processing techniques. The germanium elements are subsequently formed overlying the silicon by epitaxial growth. The germanium elements are advantageously grown within surface openings of a dielectric cladding. Wafer processing techniques are applied to the elements to form isolated germanium photodiodes. Since temperatures needed for germanium processing are lower than those for silicon processing, the formation of the germanium devices need not affect the previously formed silicon devices. Insulating and metallic layers are then deposited and patterned to interconnect the silicon devices and to connect the germanium devices to the silicon circuits. The germanium elements are thus integrated to the silicon by epitaxial growth and integrated to the silicon circuitry by common metal layers.
US patent application 2006/0110844 (Jong-Jan Lee et al.) discloses a method of fabricating a thin film germanium photodetector. The method includes preparing a silicon substrate; fabricating a CMOS device on the silicon substrate; preparing a germanium substrate; preparing surfaces of each substrate for bonding; bonding the germanium substrate to the CMOS-bearing silicon substrate to form a bonded structure; removing a portion of the germanium substrate from the bonded structure; forming a PIN diode in the germanium substrate; removing a portion of the germanium layer by etching; and completing the germanium photo detector.
As is known in the art, epitaxial growth of Ge on Si substrates is hampered by the substantial difference in lattice parameters of the order of 4%. As a result of this large misfit but a few monolayers of Ge can be grown as a two-dimensional epitaxial film on a Si substrate. At larger thicknesses lattice relaxation sets in, first in elastically by way of island formation, and then plastically by means of misfit dislocations. While interfacial misfit dislocations do not necessarily have an adverse effect on device performance, the threading dislocations usually accompanying the relaxation process usually do.
Researchers have therefore been looking for ways to reduce the density of undesirable threading dislocations. A method for lowering this density turned out to be the method of grading. Here, a SiGe alloy is epitaxially grown instead of a pure Ge layer, whereby the Ge content is slowly increased as growth proceeds, until the final alloy composition is reached.
U.S. Pat. No. 5,221,413 (Brasen et al.) discloses such a grading method wherein by growing germanium-silicon alloy at high temperatures in excess of about 850° C. and increasing the germanium content at a gradient of less than about 25% per micrometer, one can grow on silicon large area heterostructures of graded GexSi1-x alloy having a low level of threading dislocation defects. With low concentrations of germanium (0.10≦x≦0.50), the heterolayer can be used as a substrate for growing strained layer silicon devices such as MOSFETS. With high concentrations of Ge (0.65≦x≦1.00) the heterolayer can be used on silicon substrates as a buffer layer for indium gallium phosphide devices such as light emitting diodes and lasers. At concentrations of pure germanium (x=1.00), the heterolayer can be used for GaAs or GaAs/AlGaAs devices. This method requires relatively thick layers for grading up to pure Ge, since the grading rate needs to be kept typically below 10%/μm in order to be effective in reducing the density of threading dislocations. For the usual deposition methods such as chemical vapour deposition (CVD) and molecular beam epitaxy (MBE) the process is therefore relatively slow.
U.S. Pat. No. 6,537,370 (Hernandez et al.) discloses a method which consists in: (a) stabilization of the monocrystalline silicon substrate temperature at a first predetermined temperature T1 of 400 to 500° C.; (b) chemical vapour deposition (CVD) of germanium at said first predetermined temperature T1 until a base germanium layer is formed on the substrate, with a predetermined thickness less than the desired final thickness; (c) increasing the CVD temperature from said first predetermined temperature T1 up to a second predetermined temperature T2 of 750 to 850° C.; and (d) carrying on with CVD of germanium at said second predetermined temperature T2 until the desired final thickness for the monocrystalline germanium final layer is obtained.
International Patent Application No. WO2004/001857 (Wada et al.) discloses a photodetector device includes a plurality of Ge epilayers that are grown on a substrate and annealed in a defined temperature range. The Ge epilayers form a tensile strained Ge layer that allows the photodetector device to operate in the C-band and L-band.
U.S. Pat. No. 7,115,895 (von Känel), which is incorporated herein by reference in its entirety, discloses a method for making a semiconductor heterostructure in a growth chamber with gas inlet comprises several steps. In a first step, a virtual substrate is formed on a silicon substrate, comprising a graded Si1-xGex layer followed by a Si1-xGex layer with a constant x, using a high-density, low-energy plasma enhanced chemical vapour deposition (LEPECVD) process. In this step, the growth rate is maintained above 2 nm/s and the substrate temperature may range from to 400° C. and 850° C. and the total reactive gas flow at the gas inlet ranging from 5 standard cubic centimetres (sccm) to 200 sccm. In another step, an active region is formed on said virtual substrate comprising a Ge-channel and a modulation-doped layer using a low-density, low-energy plasma enhanced chemical vapor deposition (LEPECVD) process. In this step, hydrogen (H2) is introduced into the growth chamber to act as a surfactant, a substrate temperature is maintained between or substantially equal to 400° C. and 500° C. and a dopant gas is introduced in a pulsed manner into the growth chamber to provide for the modulation-doped layer. LEPECVD is based on high-density, low-energy plasma generated by a low-voltage DC arc discharge. High radical densities from precursor gases cracked in the dense plasma have been shown to result in growth rates as high as 10 nm/s, far above the rates achievable by CVD at substrate temperatures below 800° C. LEPECVD is thus a suitable method for reducing growth time of thick relaxed alloy buffer layers to acceptable levels.
It will be appreciated that for simplicity and clarity of illustration, elements shown in the figures have not necessarily been drawn to scale. For example, the dimensions of some of the elements may be exaggerated relative to other elements for clarity. Further, where considered appropriate, reference numerals may be repeated among the figures to indicate identical elements but may not be referenced in the description for all figures.